The invention generally relates to a deskew architecture.
Bits of data typically are communicated over a bus via one or more data signals. In this manner, each data line of the bus communicates a data signal, and different time slices of this data signal indicates different bits of data. The bus typically includes a clock line that communicates a clock signal for purposes of indicating the time positions of the bits in the data signal so that the bits may be recovered from the data signal. The bus may include multiple clock and data lines.
As a more specific example, the clock line typically communicates a periodic clock signal that is used for purposes of indicating the time positions of the different bits of data that has edges that are created by logical state transitions of the clock signal. Each clock edge, in turn, typically is synchronized to a particular time slice (also called a “data eye”) of the data signal. In this time slice, the data signal has a logical level indicative of a particular bit of data. Thus, each clock edge is synchronized to a particular bit of data. Therefore, the clock edges typically are used to trigger sampling of the data signal to recover bits of data from a particular data signal.
Ideally, the clock and data signals maintain a predetermined phase relationship as these signals propagate along their respective bus lines. However, non-ideal effects, such as data line skewing and clock jitter, typically alter the phase relationship between the clock and data signals so that at the receiving circuitry, the clock and data signals no longer have a predetermined phase relationship. In a source synchronous clocking scheme, the transmitting circuitry that furnishes the data signal to the bus synchronizes the data and clock signals. Thus, the clock and data signals may have a predetermined phase relationship at the source, i.e., the point where the data signal is furnished to the bus. However, at the receiving circuitry, the edges of the clock signal may have a relatively unpredictable phase relationship with respect to the data signal. Thus, the clock edges cannot be used to trigger sampling of the data signal without realigning or re-synchronizing the clock and data signals.
A bus standard typically defines timing relationships between various signals of a bus. However, the bus standard may assume source synchronous clocking and thus, not define a timing relationship between the data and clock signals at the data receiving circuitry. One such bus standard is the System Packet Interface Level 4 Phase 2 (SPI-4 Phase 2) bus standard specification, such as version 2000.088.4 available from the Optical Internetworking Forum (OIF), located at 39355 California Street, Suite 307, Fremont, Calif. 94538. The SPI-4 Phase 2 bus is a 16-bit wide 400 MHz double data rate telecommunications bus that may be used to exchange packet level information between link and physical layers of a particular network protocol. Because there is no defined relationship between the data and clock signals at the data receiving interface circuitry to this bus, the data lines can be skewed by plus or minus one bit period, and clock jitter adds a fifty percent uncertainty to where the edges of the clock signals occur relative to the data signal.
Thus, there is a continuing need for an arrangement and/or technique to address one or more of the problems that are stated above as well as possibly address other problems not set forth above.